MIPI Display

MIPI Interface Display Porting


1. MIPI Porting Guide
    1.1. PAD Function Setting

    1.2. MIPI DSI

    1.3. Power

    1.4. Drivers
        1.4.1. U-BOOT
        1.4.2. KERNEL


1. MIPI Porting Guide

1.1. PAD Function Setting

PAD Alternate Function is initialized in the following files:
– U-BOOT/board/<CHIPSET>/<Target Board>/include/cfg_gpio.h
– KERNEL/arch/arm/plat-<CHIPSET>/<Target Board>/include/cfg_gpio.h

1.2. MIPI DSI

MIPI PAD do not have the Alternate Function.
– MIPIDSI_DP[0:3], MIPIDSI_DN[0:3],
– MIPIDSI_DPCLK, MIPIDSI_DNCLK, MIPIDSI_VREG_0P4V

1.3. Power

If you are using the power of NXE2000, it is set as follows:

– UBOOT

U-BOOT/board/<CHIPSET>/<Target Board>include/nxe2000_power.h

#define NXE2000_DEF_LDO3_ON 1 /* VAL = 0: Off, 1: On 1.8V SYS1 Boot On */
#define NXE2000_DEF_LDO3_VOL 1800000 /* VAL(uV) = 0: 0.90 ~ 3.5V, Step = 25mV, default(OTP) = 1.80V */

– KERNEL

KERNEL/arch/arm/plat-<CHIPSET/<Target Board>/device.c

static struct regulator_consumer_supply nxe2000_ldo3_supply_0[] = {
REGULATOR_SUPPLY(“LCD_1.8V”, NULL),
};
NXE2000_PDATA_INIT(ldo3, 0, 1000000, 3500000, 0, 0, 1800000, 0, 2); /* 1.8V LCD */


1.4. Drivers

1.4.1. U-BOOT 

– Config

U-BOOT/include/configs/<CHIPSET>_<Target Board>.h

#define CONFIG_DISPLAY_OUT
… … …
#define CONFIG_DISPLAY_OUT_MIPI

– MIPI Parameter Setting

U-BOOT/board/<CHIPSET>/<Target Board>/include/cfg_main.h

/*—————————————————————————— *
Display (DPC and MLC) */
#define CFG_DISP_OUTPUT_MODOLE 0 // 0 : Primary, 1 : Secondary
#define CFG_DISP_PRI_SCREEN_LAYER 0
#define CFG_DISP_PRI_SCREEN_RGB_FORMAT MLC_RGBFMT_A8B8G8R8
#define CFG_DISP_PRI_SCREEN_PIXEL_BYTE 4
#define CFG_DISP_PRI_SCREEN_COLOR_KEY 0x090909
#define CFG_DISP_PRI_VIDEO_PRIORITY 2 // 0, 1, 2, 3
#define CFG_DISP_PRI_BACK_GROUND_COLOR 0x0
#define CFG_DISP_PRI_MLC_INTERLACE CFALSE
#define CFG_DISP_PRI_RESOL_WIDTH 1280 // X Resolution
#define CFG_DISP_PRI_RESOL_HEIGHT 800 // Y Resolution
#define CFG_DISP_PRI_HSYNC_SYNC_WIDTH 1
#define CFG_DISP_PRI_HSYNC_BACK_PORCH 0
#define CFG_DISP_PRI_HSYNC_FRONT_PORCH 160
#define CFG_DISP_PRI_HSYNC_ACTIVE_HIGH CFALSE
#define CFG_DISP_PRI_VSYNC_SYNC_WIDTH 1
#define CFG_DISP_PRI_VSYNC_BACK_PORCH 0
#define CFG_DISP_PRI_VSYNC_FRONT_PORCH 23
#define CFG_DISP_PRI_VSYNC_ACTIVE_HIGH CFALSE
#define CFG_DISP_PRI_CLKGEN0_SOURCE DPC_VCLK_SRC_PLL2
#define CFG_DISP_PRI_CLKGEN0_DIV 12
#define CFG_DISP_PRI_CLKGEN0_DELAY 0
#define CFG_DISP_PRI_CLKGEN0_INVERT 0
#define CFG_DISP_PRI_CLKGEN1_SOURCE DPC_VCLK_SRC_VCLK2
#define CFG_DISP_PRI_CLKGEN1_DIV 1
#define CFG_DISP_PRI_CLKGEN1_DELAY 0
#define CFG_DISP_PRI_CLKGEN1_INVERT 0
#define CFG_DISP_PRI_CLKSEL1_SELECT 0
#define CFG_DISP_PRI_PADCLKSEL DPC_PADCLKSEL_VCLK /* VCLK=CLKGEN1, VCLK12=CLKGEN0 */
#define CFG_DISP_PRI_PIXEL_CLOCK 80000000/ CFG_DISP_PRI_CLKGEN0_DIV
#define CFG_DISP_PRI_OUT_SWAPRB CFALSE
#define CFG_DISP_PRI_OUT_FORMAT DPC_FORMAT_RGB666
#define CFG_DISP_PRI_OUT_YCORDER DPC_YCORDER_CbYCrY
#define CFG_DISP_PRI_OUT_INTERLACE CFALSE
#define CFG_DISP_PRI_OUT_INVERT_FIELD CFALSE
/*——————————————————————————
* LVDS
*/
#define CFG_DISP_LVDS_LCD_FORMAT LVDS_LCDFORMAT_VESA

– Driver : Please add the source code below.

U-BOOT/board/<CHIPSET>/<Target Board>/display.c

#if defined(CONFIG_DISPLAY_OUT_MIPI)
#define MIPI_BITRATE_480M
#ifdef MIPI_BITRATE_1G
#define PLLPMS 0x33E8
#define BANDCTL 0xF
#elif defined(MIPI_BITRATE_900M)
#define PLLPMS 0x2258
#define BANDCTL 0xE
#elif defined(MIPI_BITRATE_840M)
#define PLLPMS 0x2230
#define BANDCTL 0xD
#elif defined(MIPI_BITRATE_750M)
#define PLLPMS 0x43E8 #define BANDCTL 0xC
#elif defined(MIPI_BITRATE_660M)
#define PLLPMS 0x21B8
#define BANDCTL 0xB
#elif defined(MIPI_BITRATE_600M)
#define PLLPMS 0x2190
#define BANDCTL 0xA
#elif defined(MIPI_BITRATE_540M)
#define PLLPMS 0x2168
#define BANDCTL 0x9
#elif defined(MIPI_BITRATE_512M)
#define PLLPMS 0x3200
#define BANDCTL 0x9
#elif defined(MIPI_BITRATE_480M)
#define PLLPMS 0x2281
#define BANDCTL 0x8
#elif defined(MIPI_BITRATE_420M)
#define PLLPMS 0x2231
#define BANDCTL 0x7
#elif defined(MIPI_BITRATE_402M)
#define PLLPMS 0x2219
#define BANDCTL 0x7
#elif defined(MIPI_BITRATE_210M)
#define PLLPMS 0x2232
#define BANDCTL 0x4
#endif

#define PLLCTL 0
#define DPHYCTL 0
#define MIPI_DELAY 0xFF
struct data_val{
    u8 data[48];
};
struct mipi_reg_val{ // Please refer to the LCD Datasheet.
    u32 cmd; // Data Identifier (DI)
    u32 addr; // LCD Regsiter
    u32 cnt; // Data Length
    struct data_val data; // Packet Data
};
static struct mipi_reg_val mipi_init_data_tiny[]= // Init code is obtained from the LCD company.
{
    {MIPI_DELAY, 5, 0, {0}},
    {0x39, 0xF0, 2, {0x5A, 0x5A}},
    {0x39, 0xD0, 2, {0x00, 0x10}},
    {MIPI_DELAY, 1, 0, {0}},
    {0x39, 0xC3, 3, {0x40, 0x00, 0x28}},
    {MIPI_DELAY, 5, 0, {0}},
    {0x05, 0x00, 1, {0x11}},
    {MIPI_DELAY,120, 0, {0}},
    {0x39, 0xF0, 2, {0x5A, 0x5A}},
    {0x15, 0x35, 1, {0x00}},
    {0x05, 0x00, 1, {0x29}},
};
static void mipilcd_dcs_long_write(U32 cmd, U32 ByteCount, U8* pByteData)
{
    U32 DataCount32 = (ByteCount+3)/4;
    int i = 0;
    U32 index = 0;
    volatile NX_MIPI_RegisterSet* pmipi = (volatile NX_MIPI_RegisterSet*)IO_ADDRESS(NX_MIPI_GetPhysicalAddress(index));
    NX_ASSERT( 512 >= DataCount32 );
    for( i=0; i<DataCount32; i++ )
    {
       pmipi->DSIM_PAYLOAD = (pByteData[3]<<24)|(pByteData[2]<<16)|(pByteData[1]<<8)|pByteData[0];
       pByteData += 4;
    }
    pmipi->DSIM_PKTHDR = (cmd & 0xff) | (ByteCount<<8);
}
static void mipilcd_dcs_write( unsigned int id, unsigned int data0, unsigned int data1 )
{
    U32 index = 0;
    volatile NX_MIPI_RegisterSet* pmipi = (volatile NX_MIPI_RegisterSet*)IO_ADDRESS(NX_MIPI_GetPhysicalAddress(index));
    pmipi->DSIM_PKTHDR = id | (data0<<8) | (data1<<16);
}
static int MIPI_LCD_INIT(int width, int height, void *data)
{
    int i=0;
    U32 index = 0;
    U32 value = 0;
    u8 pByteData[48];
    int size = ARRAY_SIZE(mipi_init_data);
    volatile NX_MIPI_RegisterSet* pmipi = (volatile NX_MIPI_RegisterSet*)IO_ADDRESS(NX_MIPI_GetPhysicalAddress(index));
    value = pmipi->DSIM_ESCMODE;
    pmipi->DSIM_ESCMODE = value|(3 << 6);
    value = pmipi->DSIM_ESCMODE;
    mdelay(10);
    for(i=0; i<size; i++)
    {
        switch(mipi_init_data[i].cmd)
       {
        case 0x05:
          mipilcd_dcs_write(mipi_init_data[i].cmd, mipi_init_data[i].data.data[0], 0x00);
           break;
       case 0x15:
           mipilcd_dcs_write(mipi_init_data[i].cmd, mipi_init_data[i].addr, mipi_init_data[i].data.data[0]);
          break;
        case 0x39:
          pByteData[0] = mipi_init_data[i].addr; memcpy(&pByteData[1], &mipi_init_data[i].data.data[0], 48);
          mipilcd_dcs_long_write(mipi_init_data[i].cmd, mipi_init_data[i].cnt+1, &pByteData[0]);
           break;
        case MIPI_DELAY:
          mdelay(mipi_init_data[i].addr);
          break;
        }
    mdelay(1);
    }
    value = pmipi->DSIM_ESCMODE;
    pmipi->DSIM_ESCMODE = value&(~(3 << 6));
    value = pmipi->DSIM_ESCMODE; mdelay(10);
    return 0;
}
#endif

#define INIT_VIDEO_SYNC(name) \
struct disp_vsync_info name = { \
    .h_active_len = CFG_DISP_PRI_RESOL_WIDTH, \
    .h_sync_width = CFG_DISP_PRI_HSYNC_SYNC_WIDTH, \
    .h_back_porch = CFG_DISP_PRI_HSYNC_BACK_PORCH, \
    .h_front_porch = CFG_DISP_PRI_HSYNC_FRONT_PORCH, \
    .h_sync_invert = CFG_DISP_PRI_HSYNC_ACTIVE_HIGH, \
    .v_active_len = CFG_DISP_PRI_RESOL_HEIGHT, \
    .v_sync_width = CFG_DISP_PRI_VSYNC_SYNC_WIDTH, \
    .v_back_porch = CFG_DISP_PRI_VSYNC_BACK_PORCH, \
    .v_front_porch = CFG_DISP_PRI_VSYNC_FRONT_PORCH, \
    .v_sync_invert = CFG_DISP_PRI_VSYNC_ACTIVE_HIGH, \
    .pixel_clock_hz = CFG_DISP_PRI_PIXEL_CLOCK, \
    .clk_src_lv0 = CFG_DISP_PRI_CLKGEN0_SOURCE, \
    .clk_div_lv0 = CFG_DISP_PRI_CLKGEN0_DIV, \
    .clk_src_lv1 = CFG_DISP_PRI_CLKGEN1_SOURCE, \
    .clk_div_lv1 = CFG_DISP_PRI_CLKGEN1_DIV, \
};
#define INIT_PARAM_SYNCGEN(name) \
struct disp_syncgen_param name = { \
    .interlace = CFG_DISP_PRI_MLC_INTERLACE, \
    .out_format = CFG_DISP_PRI_OUT_FORMAT, \
    .lcd_mpu_type = 0, \
    .invert_field = CFG_DISP_PRI_OUT_INVERT_FIELD, \
    .swap_RB = CFG_DISP_PRI_OUT_SWAPRB, \
    .yc_order = CFG_DISP_PRI_OUT_YCORDER, \
    .delay_mask = 0, \
    .vclk_select = CFG_DISP_PRI_PADCLKSEL, \
    .clk_delay_lv0 = CFG_DISP_PRI_CLKGEN0_DELAY, \
    .clk_inv_lv0 = CFG_DISP_PRI_CLKGEN0_INVERT, \
    .clk_delay_lv1 = CFG_DISP_PRI_CLKGEN1_DELAY, \
    .clk_inv_lv1 = CFG_DISP_PRI_CLKGEN1_INVERT, \
    .clk_sel_div1 = CFG_DISP_PRI_CLKSEL1_SELECT, \
};
#define INIT_PARAM_MULTILY(name) \
struct disp_multily_param name = { \
    .x_resol = CFG_DISP_PRI_RESOL_WIDTH, \
    .y_resol = CFG_DISP_PRI_RESOL_HEIGHT, \
    .pixel_byte = CFG_DISP_PRI_SCREEN_PIXEL_BYTE, \
    .fb_layer = CFG_DISP_PRI_SCREEN_LAYER, \
    .video_prior = CFG_DISP_PRI_VIDEO_PRIORITY, \
    .mem_lock_size = 16, \
    .rgb_format = CFG_DISP_PRI_SCREEN_RGB_FORMAT, \
    .bg_color = CFG_DISP_PRI_BACK_GROUND_COLOR, \
    .interlace = CFG_DISP_PRI_MLC_INTERLACE, \
};
#define INIT_PARAM_LVDS(name) \
struct disp_lvds_param name = { \
    .lcd_format = CFG_DISP_LVDS_LCD_FORMAT,\
};
#define INIT_PARAM_RGB(name) \
struct disp_rgb_param name = { \
    .lcd_mpu_type = 0, \
};
#define INIT_PARAM_MIPI(name) \
struct disp_mipi_param name = { \
    .pllpms = PLLPMS, \
    .bandctl = BANDCTL, \
    .pllctl = PLLCTL, \
    .phyctl = DPHYCTL, \
    .lcd_init = MIPI_LCD_INIT \
};

int bd_display(void)
{
    INIT_VIDEO_SYNC(vsync);
    INIT_PARAM_SYNCGEN(syncgen);
    INIT_PARAM_MULTILY(multily);
#if defined(CONFIG_DISPLAY_OUT_MIPI)
    INIT_PARAM_MIPI(mipi);
    /* set syncgen parameters */
    syncgen.delay_mask = DISP_SYNCGEN_DELAY_RGB_PVD | DISP_SYNCGEN_DELAY_HSYNC_CP1 |
                                             DISP_SYNCGEN_DELAY_VSYNC_FRAM | DISP_SYNCGEN_DELAY_DE_CP;
    syncgen.d_rgb_pvd = 0;
    syncgen.d_hsync_cp1 = 0;
    syncgen.d_vsync_fram = 0;
    syncgen.d_de_cp2 = 7;
    syncgen.vs_start_offset = (vsync.h_front_porch + vsync.h_sync_width + vsync.h_back_porch + vsync.h_active_len – 1);
    syncgen.ev_start_offset = (vsync.h_front_porch + vsync.h_sync_width + vsync.h_back_porch + vsync.h_active_len – 1);
    syncgen.vs_end_offset = 0; syncgen.ev_end_offset = 0;
    lcd_draw_boot_logo(CONFIG_FB_ADDR, multily.x_resol, multily.y_resol, multily.pixel_byte);
    display_mipi(CFG_DISP_OUTPUT_MODOLE, CONFIG_FB_ADDR, &vsync, &syncgen, &multily, &mipi);
#endif
    return 0;
}

U-BOOT/arch/arm/cpu/slsiap/devices/display_mipi.c
U-BOOT/arch/arm/cpu/slsiap/devices/display_dev.c
… … …

 


1.4.2. KERNEL

– Check the config needed in Kernel menuconfig.

KERNEL$ make ARCH=arm menuconfig

PWM config
System Type ->
[*] PWM driver
[*] /sys/devices/platform/pwm.N (sysfs interface)
[*] pwm 0
[*] pwm 1
MLC/DPC config
System Type ->
[*] Support Display SoC // CONFIG_NXP_DISPLAY
[*] Primary display output (MLC0/DPC0) // CONFIG_NXP_DISPLAY_1ST
[ ] Secondary display output (MLC1/DPC1) // CONFIG_NXP_DISPLAY_2ST
Nexell Graphics config
Device Drivers ->
Graphics support ->
[*] Backlight & LCD device support -> // CONFIG_BACKLIGHT_LCD_SUPPORT
<*> Lowlevel Backlight controls // CONFIG_BACKLIGHT_CLASS_DEVICE
<*> Generic PWM based Backlight Driver // CONFIG_BACKLIGHT_PWM
Nexell Graphics ->
[*] Allocate framebuffer with ION // CONFIG_FB_NXP_ION_MEM
[*] Support primary frame buffer (/dev/fb0) // CONFIG_FB0_NXP
(0) Display Out [0/1] // CONFIG_FB0_NXP_DISPOUT
[ ] Support secondary frame buffer (/dev/fb1) // CONFIG_FB1_NXP
[*] MIPI // CONFIG_NXP_DISPLAY_MIPI
(0) Display In [0=Display 0, 1=Display 1] // CONFIG_NXP_DISPLAY_MIPI_IN

– Platform Data
MIPI Parameter Setting

KERNEL/arch/arm/plat-<CHIPSET>/<Target Board>/include/cfg_main.h

Please refer parameter of U-BOOT.

    Platform Data : Please add the source code below.

KERNEL/arch/arm/plat-<CHIPSET>/<Target Board>/device.c

/*——————————————————————————
* DISPLAY MIPI device
*/
#if defined (CONFIG_NEXELL_DISPLAY_MIPI)
#include <linux/delay.h>
#define MIPI_BITRATE_480M
#ifdef MIPI_BITRATE_1G
#define PLLPMS 0x33E8
#define BANDCTL 0xF
#elif defined(MIPI_BITRATE_900M)
#define PLLPMS 0x2258
#define BANDCTL 0xE
#elif defined(MIPI_BITRATE_840M)
#define PLLPMS 0x2230
#define BANDCTL 0xD
#elif defined(MIPI_BITRATE_750M)
#define PLLPMS 0x43E8
#define BANDCTL 0xC
#elif defined(MIPI_BITRATE_660M)
#define PLLPMS 0x21B8
#define BANDCTL 0xB
#elif defined(MIPI_BITRATE_600M)
#define PLLPMS 0x2190
#define BANDCTL 0xA
#elif defined(MIPI_BITRATE_540M)
#define PLLPMS 0x2168
#define BANDCTL 0x9
#elif defined(MIPI_BITRATE_512M)
#define PLLPMS 0x3200
#define BANDCTL 0x9
#elif defined(MIPI_BITRATE_480M)
#define PLLPMS 0x2281
#define BANDCTL 0x8
#elif defined(MIPI_BITRATE_420M)
#define PLLPMS 0x2231
#define BANDCTL 0x7
#elif defined(MIPI_BITRATE_402M)
#define PLLPMS 0x2219
#define BANDCTL 0x7
#elif defined(MIPI_BITRATE_210M)
#define PLLPMS 0x2232
#define BANDCTL 0x4
#endif

#define PLLCTL 0

#define DPHYCTL 0
#define MIPI_DELAY 0xFF
    struct data_val{
    u8 data[48];
};
struct mipi_reg_val{ // Please refer to the LCD Datasheet.
    u32 cmd; // Data Identifier (DI)
    u32 addr; // LCD Regsiter
    u32 cnt; // Data Length
    struct data_val data; // Packet Data
};
static struct mipi_reg_val mipi_init_data_tiny[]= // init code
{
    {MIPI_DELAY, 5, 0, {0}},
    {0x39, 0xF0, 2, {0x5A, 0x5A}},
    {0x39, 0xD0, 2, {0x00, 0x10}},
    {MIPI_DELAY, 1, 0, {0}},
    {0x39, 0xC3, 3, {0x40, 0x00, 0x28}},
    {MIPI_DELAY, 5, 0, {0}},
    {0x05, 0x00, 1, {0x11}},
    {MIPI_DELAY,120, 0, {0}},
    {0x39, 0xF0, 2, {0x5A, 0x5A}},
    {0x15, 0x35, 1, {0x00}},
    {0x05, 0x00, 1, {0x29}},
};
static void mipilcd_dcs_long_write(U32 cmd, U32 ByteCount, U8* pByteData)
{
    U32 DataCount32 = (ByteCount+3)/4;
    int i = 0;
    U32 index = 0;
    volatile NX_MIPI_RegisterSet* pmipi =
    (volatile NX_MIPI_RegisterSet*)IO_ADDRESS(NX_MIPI_GetPhysicalAddress(index));
    NX_ASSERT( 512 >= DataCount32 );
    for( i=0; i<DataCount32; i++ )
    {
       pmipi->DSIM_PAYLOAD = (pByteData[3]<<24)|(pByteData[2]<<16)|(pByteData[1]<<8)|pByteData[0];
       pByteData += 4;
    }
    pmipi->DSIM_PKTHDR = (cmd & 0xff) | (ByteCount<<8);
}
static void mipilcd_dcs_write( unsigned int id, unsigned int data0, unsigned int data1 )
{
    U32 index = 0;
    volatile NX_MIPI_RegisterSet* pmipi =
    (volatile NX_MIPI_RegisterSet*)IO_ADDRESS(NX_MIPI_GetPhysicalAddress(index));
    pmipi->DSIM_PKTHDR = id | (data0<<8) | (data1<<16);
}
static int MIPI_LCD_INIT(int width, int height, void *data)
{
    int i=0;
    U32 index = 0;
    U32 value = 0;
    u8 pByteData[48];
    int size=ARRAY_SIZE(mipi_init_data);
    volatile NX_MIPI_RegisterSet* pmipi =
    (volatile NX_MIPI_RegisterSet*)IO_ADDRESS(NX_MIPI_GetPhysicalAddress(index));
    value = pmipi->DSIM_ESCMODE;
    pmipi->DSIM_ESCMODE = value|(3 << 6);
    value = pmipi->DSIM_ESCMODE;
    mdelay(10);
    for(i=0; i<size; i++)
    {
       switch(mipi_init_data[i].cmd)
       {
       case 0x05:
          mipilcd_dcs_write(mipi_init_data[i].cmd, mipi_init_data[i].data.data[0], 0x00);
          break;
       case 0x15:
          mipilcd_dcs_write(mipi_init_data[i].cmd, mipi_init_data[i].addr, mipi_init_data[i].data.data[0]);
          break;
       case 0x39:
          pByteData[0] = mipi_init_data[i].addr;
          memcpy(&pByteData[1], &mipi_init_data[i].data.data[0], 48);
          mipilcd_dcs_long_write(mipi_init_data[i].cmd, mipi_init_data[i].cnt+1, &pByteData[0]);
          break;
       case MIPI_DELAY:
          mdelay(mipi_init_data[i].addr);
          break;
       }
    mdelay(1);
    }
    value = pmipi->DSIM_ESCMODE;
    pmipi->DSIM_ESCMODE = value&(~(3 << 6));
    value = pmipi->DSIM_ESCMODE;
    mdelay(10);
    return 0;
}
static struct disp_vsync_info mipi_vsync_param = {
    .h_active_len = CFG_DISP_PRI_RESOL_WIDTH,
    .h_sync_width = CFG_DISP_PRI_HSYNC_SYNC_WIDTH,
    .h_back_porch = CFG_DISP_PRI_HSYNC_BACK_PORCH,
    .h_front_porch = CFG_DISP_PRI_HSYNC_FRONT_PORCH,
    .h_sync_invert = CFG_DISP_PRI_HSYNC_ACTIVE_HIGH,
    .v_active_len = CFG_DISP_PRI_RESOL_HEIGHT,
    .v_sync_width = CFG_DISP_PRI_VSYNC_SYNC_WIDTH,
    .v_back_porch = CFG_DISP_PRI_VSYNC_BACK_PORCH,
    .v_front_porch = CFG_DISP_PRI_VSYNC_FRONT_PORCH,
    .v_sync_invert = CFG_DISP_PRI_VSYNC_ACTIVE_HIGH,
    .pixel_clock_hz = CFG_DISP_PRI_PIXEL_CLOCK,
    .clk_src_lv0 = CFG_DISP_PRI_CLKGEN0_SOURCE,
    .clk_div_lv0 = CFG_DISP_PRI_CLKGEN0_DIV,
    .clk_src_lv1 = CFG_DISP_PRI_CLKGEN1_SOURCE,
    .clk_div_lv1 = CFG_DISP_PRI_CLKGEN1_DIV,
};
static struct disp_syncgen_par mipi_syncgen_param = {
    .delay_mask = DISP_SYNCGEN_DELAY_RGB_PVD |
                               DISP_SYNCGEN_DELAY_HSYNC_CP1 |
                               DISP_SYNCGEN_DELAY_VSYNC_FRAM |
                               DISP_SYNCGEN_DELAY_DE_CP,
    .d_rgb_pvd = 0,
    .d_hsync_cp1 = 0,
    .d_vsync_fram = 0,
    .d_de_cp2 = 7,
    .vs_start_offset = CFG_DISP_PRI_HSYNC_FRONT_PORCH +
                                  CFG_DISP_PRI_HSYNC_SYNC_WIDTH +
                                  CFG_DISP_PRI_HSYNC_BACK_PORCH +
                                  CFG_DISP_PRI_RESOL_WIDTH – 1,
    .ev_start_offset = CFG_DISP_PRI_HSYNC_FRONT_PORCH +
                                  CFG_DISP_PRI_HSYNC_SYNC_WIDTH +
                                  CFG_DISP_PRI_HSYNC_BACK_PORCH +
                                  CFG_DISP_PRI_RESOL_WIDTH – 1,
    .vs_end_offset = 0,
    .ev_end_offset = 0,
};
static struct disp_mipi_param mipi_param = {
    .pllpms = PLLPMS,
    .bandctl = BANDCTL,
    .pllctl = PLLCTL,
    .phyctl = DPHYCTL,
    .lcd_init = MIPI_LCD_INIT
};
#endif

/*——————————————————————————
* register board platform devices
*/
void __init nxp_board_devices_register(void)
{
    printk(“[Register board platform devices]\n”);
    … … …
#if defined (CONFIG_FB_NXP)
    printk(“plat: add framebuffer\n”);
    platform_add_devices(fb_devices, ARRAY_SIZE(fb_devices));
#endif
#if defined (CONFIG_NXP_DISPLAY_MIPI)
    nxp_platform_disp_device_data(DISP_DEVICE_MIPI, &mipi_vsync_param, (void*)&mipi_param, &mipi_syncgen_param);
#endif
    … … …
#if defined(CONFIG_BACKLIGHT_PWM)
    printk(“plat: add backlight pwm device\n”);
    platform_device_register(&bl_plat_device);
#endif
    … … …
}


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